Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 159)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 159
Features:
 65536 channel non blocking timeslot interchanger (TSI) with all connected interfaces on
input and output side exactly in phase to the TSI with respect to framestart. Adjustable Idle
pattern per channel.
 Fixed symmetrically mapping of framer and Dsp channel at TSI-input and output side. One
superset mapping by TSI channel supervisor allowing all applications (8xOC3, 24xDS3 and
48xT1/E1).
 Open concept allowing the use of successor DSPs and submodules (DSP-part of superset
mapping of TSI-channel supervisor has to be adapted to new DSP and submodule
structure).
 PCI-Express 1.0 (x1) interface to a host processor.
 Message based interrupts via PCI-Express to the host internal sources and from connected
framers and other components. The status of the individual interrupt sources is maskable
and readable.
 3x2.5Gbit/s(x1) or 3x2x1.25Gbit/s(x1) speech payload SERDES interfaces to DSP-FPGA
counterparts. The data transmission quality is monitored by a CRC check per packet and a
host readable and resetable error counter per link and direction. The data is realigned to
the 8kHz TDM-system frame sync at receive side.
 2x77.76MHz SBI interfaces to SONET/SDH-framers. Adjustment of SBI drop interface
frame and frame sync to TSI frame phase.
 2x77.76MHz Transport-Overhead Drop/Add interfaces to SONET/SDH-framers.
 6x HMVIP interfaces to E1/T1 framers.
 GR08 signaling generator and receiver for 768 channels via TSI in cooperation with host
DMA.
 Pattern transmission (feed-in and reception) at each SERDES interface between TSI-FPGA
and DSP-FPGAs via supplemental channels.
 Static and Pseudo random pattern generator and comparator at independently
programmable channels at TSI-input and -output side.
 SPI interface to control other components outside the FPGA, e.g. a Bits-clock-element.
 SPI-interface which is connected to an I/O-Extender PLD. The sideband signals of the
framers and other components are connected to this PLD and are imaged automatically
between the TSI-FPGA and the PLD.