Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 149)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 149
When at least one bit of Table ARTM Telecom Clock Monitor Status Register is set the
corresponding status bit CLK_MONITOR_FINISHED of Table ARTM Interrupt Group Status is
also set.
When at least one bit of Table Telecom Clock Monitor Out of Range Register is set the
corresponding status bit CLK_MONITOR_OUT_OF_RANGE of Table ARTM Interrupt Group
Status is also set.
Table 8-57 ARTM Telecom Clock Monitor Status Register
Address: 0x23
Bit Description Default Access
1:0 Result available for supervised Telecom Clocks 0 and 1
Corresponding bit is set when measurement has finished.
Clearing bit triggers new measurement. 0 RTM: r/w1c
7:2 Reserved 0 r
Table 8-58 Telecom Clock Monitor Out of Range Register
Address: 0x24
Bit Description Default Access
1:0 Frequency of supervised Telecom Clocks 0 and 1 is out of range.
Corresponding bit is set when the number of positive clock edges
within the selected time base is:
< Lower limit or
> Upper limit
Clearing bit triggers new sequence of measurements. 0 RTM: r/w1c
7:2 Reserved 0 r