Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 198)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 198
9.5.2.2.2 Gr8 Receive Data Memory
Addresses0x50000 ... 0x50FFF: Gr8RcvDatMem0 ... Gr8RcvDatMem1023
Holds the receive data for 672 Gr8 via Sonet/Sdh and 48 Gr8 channels via Exar T1 Framers. Is
copied to host memory by means of host DMA in 9ms intervals, the host is triggered by
interrupt (see General Registers Component Event Register). The actual memory has the
double of the needed size, always one half is visible to the SW during an interval, the other half
is accessed by HW. In the next interval the two memory halves are interchanged, thus
decoupling SW from HW ensuring enough processing time for SW.
The cells contain the Receive Concentrator Field and Receive Maintenance., Alarm, Protection
Switch Fields of the channels.
19..
.16 Gr8TrmPrtSwFld RW These bits contain the bits to be
inserted in the protection switch field
of the next outgoing data link
message for the associated channel.
S1 corresponds to bit 16, S4
corresponds to bit 19 undef - -
15..
.14 Gr8TrmAlrmFld RW These bits contain the bits to be
inserted in the alarm field of the next
outgoing data link message for the
associated channel. A1 corresponds to
bit 14, A2 corresponds to bit 15 undef - -
13..
.11 Gr8TrmMaintFld RW These bits contain the bits to be
inserted in the maintenance field of
the next outgoing data link message
for the associated channel. M1
corresponds to bit 11, M3
corresponds to bit 13 undef - -
10..
.0 Gr8TrmCncntrFld RW These bits contain the value to be
inserted in the concentrator field of
the next outgoing data link message
for the associated channel. C1
corresponds to bit 0, C11 corresponds
to bit 10 undef - -
Bit Acronym Type
Description
Default
Pwr Soft