beautypg.com

Tsi fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual

Page 239

background image

TSI FPGA

ARTM-831X Installation and Use (6806800M76E)

239

27

Spi2BusRdyTmOutIn
trptMask

RW

0b1: Spi2BusRdyTmOutEnable,
enables ready timeout at Spi bus 2
indicator

0b0

X

X

26

Spi1BusRdyTmOutIn
trptMask

RW

0b1: Spi1BusRdyTmOutEnable,
enables ready timeout at Spi bus 1
indicator

0b0

X

X

25

-

-

reserved

undef

-

-

24

LcBusRdyTmOutIntr
ptMask

RW

0b1: LcBusRdyTmOutEnable, enables
ready timeout at local bus indicator

0b0

X

X

23

ParErrDrpSbi1Intrpt
Mask

RW

0b1: ParErrDrpSbi1Enable, enables
parity error in SBI drop data from
Sonet/Sdh-framer1 indicator

0b0

X

X

22

ParErrDrpSbi0Intrpt
Mask

RW

0b1: ParErrDrpSbi0Enable, enables
parity error in SBI drop data from
Sonet/Sdh-framer0 indicator

0b0

X

X

21

SerdesRcvErrorIntrpt
Mask2

RW

0b1: SerdesRcvErrorEnable2, enables
the serdes receiver2 error indicator

0b0

X

X

20

SerdesRcvErrorIntrpt
Mask1

RW

0b1: SerdesRcvErrorEnable1, enables
the serdes receiver1 error indicator

0b0

X

X

19

SerdesRcvErrorIntrpt
Mask0

RW

0b1: SerdesRcvErrorEnable0, enables
the serdes receiver0 error indicator

0b0

X

X

18

SerdesTrmErrorIntrpt
Mask2

RW

0b1: SerdesTrmErrorEnable2, enables
the serdes receiver2 error indicator

0b0

X

X

17

SerdesTrmErrorIntrpt
Mask1

RW

0b1: SerdesTrmErrorEnable1, enables
the serdes receiver1 error indicator

0b0

X

X

16

SerdesTrmErrorIntrpt
Mask0

RW

0b1: SerdesTrmErrorEnable0, enables
the serdes receiver0 error indicator

0b0

X

X

15

NoTTPohFrameSync
1IntrptMask

RW

0b1: NoTTPohFrameSync1Enable,
enables no transmit transport path
overhead frame sync pulse from
Sonet/Sdh-framer1 indicator

0b0

X

X

14

NoTTPohFrameSync
0IntrptMask

RW

0b1: NoTTPohFrameSync0Enable,
enables no transmit transport path
overhead frame sync pulse from
Sonet/Sdh-framer0 indicator

0b0

X

X

Bit

Acronym

Type

Description
Default

Pwr

Soft