Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 84)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 84
4.4.1.3 PCIexpress x1 Interface
To provide a hi-bandwidth link to the host processor, a PCIexpress x1 Interface is available at
the TSI-FPGA device. It is routed to the front board via the upper mezzanine connector and the
zone 3 connector on the ARTM-831X base unit.
4.4.1.4 Local Bus
To provide host access to the Framer and LIU devices, the TSI-FPGA integrates a PCIexpress to
Local Bus Bridge. The Local Bus Interface is an asynchronous, parallel, non-multiplexed,
memory mapped interface for I/O read and write operations according to Intel bus mode. The
data bus width is 16Bit.
4.4.1.5 TSIP2 SERDES Interface
The data transport for the TDM channels happens via the proprietary TSIP interface. To reduce
pin count, the TSI-FPGA employs a hi-speed serialized interface (TSIP-to-SerDes) unit. Three
separate SerDes lanes are available to support the front board DSP module slots (onboard and
2 expansion slots).
The SerDes lanes are operating at 2.5Gbit/s and provide a capacity of 60 512 channels.
The SerDes I/F is routed to the front board via the upper mezzanine connector and the zone 3
connector on the ARTM-831X base unit.
4.4.1.6 Register Description
For details, see Chapter 9, TSI FPGA, on page 157