Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 75)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 75
4.3.1 TSI FPGA
The following key features are provided by the TSI FPGA device on the E1/T1 mezzanine
expansion unit:
 64k TDM channels interchange management
Provides GR8 message handling for T1 lines
 Pass on synchronous system clocks to the particular EXAR framer devices
 TSIP2SerDes conversion for front board communication
 PCIe x1 host interface & bridge to local bus
 12x HMVIP interfaces to E1/T1 Framers
Pre-select reference clock from E1/T1 framer devices 0/1
 Update/failback SPI configuration Flash in working/golden mode#
4.3.1.1 SPI Interface
The TSI- FPGA on the E1/T1 mezzanine expansion unit has three SPI interfaces in total that are
configured as point-to-point connection each:
The first one is routed via the upper mezzanine connector to the ARTM-831X_base unit and
connected to the FPGA_base device. It allows access to the mezzanine expansion section of
this FPGA_base device.
The second one is routed to its companion, the TSI- extender FPGA. It allows transparent access
to the registers in this device and thus the connected signals.
The third SPI is used for configuration and connects to a SPI Flash device.
For details, see Figure "ARTM-831X SPI Bus & RESET Structure" on page 65 .