Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 314)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 314
Width: 32 bit
The bits of this register mask the bits of the Xrt86LineEvtReg for the generation of an interrupt
to the host.
Bit Acronym Type Description Default Pwr Soft
31 Xrt86Chp5RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable7,
enables chip 5 receiver Line 7 loss
of signal interrupt 0b0 X X
30 Xrt86Chp5RcvLoSIntrpt
Mask6 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable6,
enables chip 5 receiver Line 6 loss
of signal interrupt 0b0 X X
29 Xrt86Chp5RcvLoSIntrpt
Mask5 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable5,
enables chip 5 receiver Line 5 loss
of signal interrupt 0b0 X X
28 Xrt86Chp5RcvLoSIntrpt
Mask4 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable4,
enables chip 5 receiver Line 4 loss
of signal interrupt 0b0 X X
27 Xrt86Chp5RcvLoSIntrpt
Mask3 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable3,
enables chip 5 receiver Line 3 loss
of signal interrupt 0b0 X X
26 Xrt86Chp5RcvLoSIntrpt
Mask2 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable2,
enables chip 5 receiver Line 2 loss
of signal interrupt 0b0 X X
25 Xrt86Chp5RcvLoSIntrpt
Mask1 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable1,
enables chip 5 receiver Line 1 loss
of signal interrupt 0b0 X X
24 Xrt86Chp5RcvLoSIntrpt
Mask0 RW 0b1:
Xrt86Chp5RcvLoSIntrptEnable0,
enables chip 5 receiver Line 0 loss
of signal interrupt 0b0 X X