Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 67)

Functional Description
ARTM-831X Installation and Use (6806800M76E) 67
4.2.1.1 SPI Interface
The FPGA_base device on the ARTM base has 4 individual SPI interfaces in total. See Figure
"ARTM-831X SPI Bus & RESET Structure" on page 65 .
The first one is a point-to-point SPI routed from the Front board FPGA via zone 3. It belongs to
the IP section of the device and provides the basic access and control from the host side.
The second SPI is also p2p configured and connects to a SPI FLASH device. It is used for
configuration of the FPGA.
The third SPI belongs to the TDM expansion section. It connects to both BITS framer devices via
chip select signals and provides host access and control functionality.
The fourth SPI is again p2p configured and connects the TDM expansion section to TSI-FPGA
when a mezzanine card is installed. The TSI-FPGA is the master in this configuration.IP/BITS
Overhead Signals.