Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 298)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 298
0x30
0x40
0x50
0x60 Xrt75LineEvtReg0
Xrt75LineEvtReg1
Xrt75LineEvtReg2
Xrt75LineEvtReg3 Xrt75 Line Interface Line Event Register (32bit) [Hw: syn,
WAck1, RAck1]
This registers monitor the loss of signal outputs of the
Xrt75 framer chips 0..3 If a loss of signal occurs, the
respective bit is set. It can be reset by writing the respective
bit in Xrt75LineEvtResReg.
This registers monitor the loss of lock outputs of the Xrt75
framer chips 0..3 If a loss of lock indicators occurs, the
respective bit is set. It can be reset by writing the respective
bit in Xrt75LineEvtResReg.
This registers monitor the loss of lock outputs of the Xrt75
framer chips 0..3 If a drive monitor output failure occurs,
the respective bit is set. It can be reset by writing the
respective bit in Xrt75LineEvtResReg.
0x34
0x44
0x54
0x64 Xrt75LineEvtResReg0
Xrt75LineEvtResReg1
Xrt75LineEvtResReg2
Xrt75LineEvtResReg3 Xrt75 Line Interface Line Event Reset Register (32bit) [Hw:
syn, WAck1, RAck1]
The bits of this register reset the respective bits in
Xrt75LineEvtReg. Writing a 1 to a bit in
Xrt75LineEvtResReg resets the corresponding bit in
Xrt75LineEvtReg The interrupt bit in Xrt75LineEvtReg is
kept reset until writing a 0 to the corresponding bit in
Xrt75LineEvtResReg re-enables its monitor function.again.
0x38
0x48
0x58
0x68 Xrt75LineEvtMaskReg0
Xrt75LineEvtMaskReg1
Xrt75LineEvtMaskReg2
Xrt75LineEvtMaskReg3 Xrt75 Line Interface Line Event Mask Register (32bit) [Hw:
syn, WAck1, RAck1]
The bits of this register mask the bits of the
Xrt75LineEvtReg. For the generation of an interrupt to the
host.
0x80 UnOccpdAddrMonReg Unoccupied Address Access Monitor Register (8bit) [Hw:
syn, WAck1, RAck1]
This register monitors the access to unoccupied address
areas
0x81 UnOccpdAddrMonResetRe
g Unoccupied Address Access Monitor Reset Register (8bit)
[Hw: syn , WAck1, RAck1]
This register resets the access to unoccupied address area
monitor and unoccupied address area address registers
Table 10-4 EXT FPGA Addressmap Overview (continued)