Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 310)

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ARTM-831X Installation and Use (6806800M76E) 310
10.4.2.1.9 Xrt86 Framer Line Event Status Reset Register
Address:
0x24, Xrt86LineEvtResReg
Width: 32 bit
The bits of this register reset the respective bits in Xrt86LineEvtReg. Writing a 1 to a bit in
Xrt86LineEvtResReg resets the corresponding bit in Xrt86LineEvtReg. The interrupt bit in
Xrt86LineEvtReg is kept reset until writing a 0 to the corresponding bit in Xrt86LineEvtResReg
re-enables its monitor function again.
Bit Acronym Type Description Default Pwr Soft
31 Xrt86Chp5RcvLoSIntrptR
eset7 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset7,
resets chip 5 receiver Line 7 loss
of signal indicator bit 0b0 X X
30 Xrt86Chp5RcvLoSIntrptR
eset6 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset6,
resets chip 5 receiver Line 6 loss
of signal indicator bit 0b0 X X
29 Xrt86Chp5RcvLoSIntrptR
eset5 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset5,
resets chip 5 receiver Line 5 loss
of signal indicator bit 0b0 X X
28 Xrt86Chp5RcvLoSIntrptR
eset4 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset4,
resets chip 5 receiver Line 4 loss
of signal indicator bit 0b0 X X
27 Xrt86Chp5RcvLoSIntrptR
eset3 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset3,
resets chip 5 receiver Line 3 loss
of signal indicator bit 0b0 X X
26 Xrt86Chp5RcvLoSIntrptR
eset2 RW 0b1:
Xrt86Chp5RcvLoSIntrptReset2,
resets chip 5 receiver Line 2 loss
of signal indicator bit 0b0 X X