Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 206)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 206
The input channel 0 of the Tsi is connected to this registerCnctRegs are written with the value
of this register when initialization is started by TsiInitReg
9.5.2.4.5 Tsi Channel Counter Register
Address:
0x1010, TsiChnCntReg
Width: 32 bit
The TsiChnCntReg shows the currently processed channels by the Tsi and increments in steps
of 4, since 4 channels are always processed during the same period of time. There is no action
with the Tsi where this register has to be considered.
9.5.2.5 Gr8 Registers (Gr8Regs)
Resets:
Pwr = Power on reset
Soft = Soft reset
Gr8 Control and Status Register
Bit Acronym Type
Description
Default
Pwr Soft
31..
.18 - - reserved undef - -
7...
0 TsiCh0InputDataReg RW Value for data sent into Tsi channel 0
input 0b0 X X
Bit Acronym Type
Description
Default
Pwr Soft
31..
.16 - - reserved undef - -
15..
.0 TsiChnCnt R first of 4 consecutive currently
processed channels 0b0 F F