Figure 4-5, Artm-831x spi bus & reset structure, Functional description – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 65: Rtm_base, Rtm_mezzanine
Functional Description
ARTM-831X Installation and Use (6806800M76E)
65
Figure 4-5
ARTM-831X SPI Bus & RESET Structure
XRT75
06D
XRT75
06D
XRT75
06D
PM8310
XRT86
VX38
XRT86
VX38
XRT86
VX38
XRT86
VX38
XRT86
VX38
BCM8707
DS26503
RTM-
FPGA
(base)
SPI
Flash
Config
SPI
SPI-Bus
from front board
FPGA (clock
master)
TSI-FPGA
SPI
Flash
Config
SPI
PCIe
RTM-
FPGA
TSI-X
SPI
Flash
Config
SPI
SPI-Bus
RTM_base
RTM_mezzanine
SPI-Bus
(FPGA TSI-X
clock master)
From Zone 3
c
o
nnec
to
r
RTM_RESET
DS26503
2x BITS_TSTRST
BCM
54640
RESET_BCM54640
BCM8707
2x RSTB_BCM8707
RTM_RESET
6x RESET_XRT86V38
XRT86
VX38
PM8310
XRT75
06D
2x RESET_PM8310
4x RESET_XRT7506D
SPI-Bus
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