Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 199)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 199
The cells 0...767 are prepared by Hw to receive data from Pmc8310 Sonet/Sdh Framers. A
respective Tsi connection is needed for every used channel.
The cells 768...1023 are prepared by Hw to receive data from Xrt86 Framers. The channels can
only be used in groups of four. All four channels must be switched by the Tsi to the respective
Hmvip link channel 0 of a E1/T1 framer (broadcast). The cells contain the Transmit
Concentrator Field and Transmit Maintenance., Alarm, Protection Switch Fields of the
channels.
They may be mapped as following:
The cells 0..335 match to the SBI interface 0 to PMC8310 chip 0, 336 to 671 or SBI interface 1
to PMC8310 chip 1.
Cell 0,4,8,... match to the SBI interface 0 (PMC8310 chip 0), subsystem 0, channel 0,1,2,...
Cell 1,5,9, ... match to the SBI interface 0 (PMC8310 chip 0), subsystem 1, channel 0,1,2,...
Cell 2,6,10, ... match to the SBI interface 0 (PMC8310 chip 0), subsystem 2, channel 0,1,2,...
Cell 3,7,11, ... match to the SBI interface 0 (PMC8310 chip 0), subsystem 3, channel 0,1,2,
...
Cell 336,340,344,... match to the SBI interface 1 (PMC8310 chip 1), subsystem 0, channel
0,1,2,
Cell 337,341,345, ... match to the SBI interface 1 (PMC8310 chip 1), subsystem 1, channel
0,1,2,
Cell 338,342,346, ... match to the SBI interface 1 (PMC8310 chip 1), subsystem 2, channel
0,1,2,
Cell 339,343,347, ... match to the SBI interface 1 (PMC8310 chip 1), subsystem 3, channel
0,1,2,
...
The cells 672,673 ... unused
...
The cells 768,769, ... 771 match to the T1 interface 0 (Xrt86 framer chip 0) channel 0,1,2,3,