Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 207)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 207
9.5.2.5.1 Gr8 Initialization Register
Address:
0x1040, Gr8InitReg
Width: 32 bit
The Gr8TrmMem cells are written with 0x0000 from TsiInitValReg during the first 27ms after
power-on reset, thus disabling all output channels. A re-initialization in the same manner can
be started later again by Gr8InitReg. The initialization process can be monitored with
Gr8InitMonReg.
9.5.2.5.2 Gr8 Initialization Monitor Register
Address:
0x1044, Gr8InitMonReg
Width: 32 bit
The Gr8TrmMem initialization and can be monitored (takes 18-27ms).
Bit Acronym Type
Description
Default
Pwr Soft
31..
.16 - - reserved undef - -
15..
.0 Gr8InitStart W 0xCEEC: Gr8InitStart, Write 0xCEEC to
start Tsi initialization 0b0 F F
Bit Acronym Type
Description
Default
Pwr Soft
31..
.1 - - reserved undef - -
0 Gr8InitDone R 0b1: Gr8InitDone, Tsi initialization
done after power-on reset or
initialization restart by TsiInitReg, reset
by power on or when initialization is
started by TsiInitReg 0b0 F F