Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 153)

Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E) 153
8.6.3.1 MMC I2C Slave Read Register
With the following sequence a FPGA register is read:
 Start condition
 Slave Address 0xFE and Write Command. Slave ACK.
 Register Address. The upper 3 bits are ignored. Slave ACK
 Repeated Start condition (or Stop followed by a Start condition)
 Slave Address 0xFE and Read Command. Slave ACK
 Master reads data of addressed Slave Register. Master ACK when Master wants to read data
from the following addresses or NACK when the Master wants to stop read sequence. Note:
The Slave only support single read accesses. Therefore the Master should only read one
byte. The following bytes will all be 0xFF.
 Stop condition.
8.6.3.2 MMC I2C Slave Write Register
With the following sequence a FPGA register is written:
 Start condition
 Slave Address 0xFE and Write Command. Slave ACK.
 Register Address. The upper 3 bits are ignored. Slave ACK
 Write Data. Slave ACK. When the master sends additional write data the Slave responds
with NACK, because the Slave only supports single byte write.
 Stop condition.
8.6.3.3 MMC I2C Forwarding
The selected SFP I2C Interface sees the same logic level for SDA as the MMC I2C interface. The
I2C bridge state machine listens to the I2C protocol to decode the direction flow of the
bidirectional I2C SDA signals.
8.6.3.4 MMC I2C SCL Stretching
The I2C bridge device supports SCL Stretching. Stretching can be enabled or disabled. See
Table "SFP I2C select Register" on page 131 for more details.