Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 316)

EXT FPGA
ARTM-831X Installation and Use (6806800M76E) 316
14 Xrt86Chp3RcvLoSIntrpt
Mask6 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable6,
enables chip3 receiver Line 6 loss
of signal interrupt bit 0b0 X X
13 Xrt86Chp3RcvLoSIntrpt
Mask5 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable5,
enables chip3 receiver Line 5 loss
of signal interrupt bit 0b0 X X
12 Xrt86Chp3RcvLoSIntrpt
Mask4 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable4,
enables chip3 receiver Line 4 loss
of signal interrupt bit 0b0 X X
11 Xrt86Chp3RcvLoSIntrpt
Mask3 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable3,
enables chip3 receiver Line 3 loss
of signal interrupt bit 0b0 X X
10 Xrt86Chp3RcvLoSIntrpt
Mask2 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable2,
enables chip3 receiver Line 2 loss
of signal interrupt bit 0b0 X X
9 Xrt86Chp3RcvLoSIntrpt
Mask1 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable1,
enables chip3 receiver Line 1 loss
of signal interrupt bit 0b0 X X
8 Xrt86Chp3RcvLoSIntrpt
Mask0 RW 0b1:
Xrt86Chp3RcvLoSIntrptEnable0,
enables chip3 receiver Line 0 loss
of signal interrupt bit 0b0 X X
7 Xrt86Chp2RcvLoSIntrpt
Mask7 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable7,
enables chip 2 receiver Line 7 loss
of signal interrupt bit 0b0 X X
6 Xrt86Chp2RcvLoSIntrpt
Mask6 RW 0b1:
Xrt86Chp2RcvLoSIntrptEnable6,
enables chip 2 receiver Line 6 loss
of signal interrupt bit 0b0 X X
Bit Acronym Type Description Default Pwr Soft