Avago Technologies LSI53C1010R - Manual (Page 99)

PCI Bus Interface Signals 3-5
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.3 PCI Bus Interface Signals
The PCI Bus Interface Signals section contains tables describing the
signals for the following signal groups: System Signals; Address and
Data Signals; Interface Control Signals; Arbitration Signals; Error
Reporting Signals; Interrupt Signals.
3.3.1 System Signals
Table 3.2 describes the System Signals group.
Table 3.2 System Signals
Name Bump Type Strength Description
CLK AC9 I N/A Clock provides timing for all transactions on the PCI bus
and is an input to every PCI device and all other PCI
signals are sampled on the rising edge of CLK and other
timing parameters are defined with respect to this edge.
ENABLE66 AC2 I N/A Enable66 enable the 66 MHz PCI operation. It sets the bit
in the PCI Configuration Space indicating this device is 66
MHz capable. This pin has a static pull-up.
M66EN AC5 I N/A M66EN enables the 66 MHz PCI mode. This pin is
connected to the M66EN PCI signal on the PCI bus. If this
signal is pulled HIGH, the 66 MHz PCI operation is
enabled. This pin has a static pull-up.
Note: Pulling this signal LOW does not affect the setting of
the 66 MHz capable bit in the PCI Configuration Space.
RST/ AB10 I N/A Reset forces the PCI sequencer of each device to a known
state. All T/S and S/T/S signals are forced to a HIGH
impedance state and all internal logic is reset. The RST/
input is synchronized internally to the rising edge of CLK.
To reset the device properly, the CLK input must be active
while RST/ is active.