Scsi control four (scntl4), Register: 0xbc – Avago Technologies LSI53C1010R User Manual
Page 221
SCSI Registers
4-103
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0xBC
SCSI Control Four (SCNTL4)
Read/Write
This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.
U3EN
Ultra160 Transfer Enable
7
Setting this bit enables Ultra160 transfers. This bit forces
all SCSI Block Move SCRIPTS instructions for ST Data-In
or ST Data-Out phases to become DT Data-In or DT
Data-Out phases.
AIPCKEN
AIP Checking Enable
6
Setting this bit enables the AIP checking of the upper byte
lane of protection information during Command, Status,
and Message phases. By default, AIP codes are
generated on the SCSI bus during all asynchronous
transfers. To disable this feature, set bit 3, the Disable AIP
Code Generation bit, in
R
Reserved
[5:4]
XCLKH_DT
Extra Clock of Data Hold on DT Transfer Edge
3
Setting this bit adds a clock of data hold to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers because it affects data hold to the DT edge.
Setting this bit reduces the synchronous transfer send
rate but does not reduce the transfer rate at which the
LSI53C1010R can receive inbound REQs, ACKs or data.
Refer to
and
for a summary of
available transfer rates and to
through
for examples of how the XCLKH bits function.
Note:
This bit does not affect CRC timings.
XCLKH_ST
Extra Clock of Data Hold on ST Transfer Edge
2
Setting this bit adds a clock of data hold to synchronous
DT or ST SCSI transfers on the ST edge. This bit impacts
both ST and DT transfers because it affects data hold to
7
6
5
4
3
2
1
0
U3EN
AIPCKEN
R
XCLKH_DT XCLKH_ST XCLKS_DT XCLKS_ST
0
0
0
0
0
0
0
0