Avago Technologies LSI53C1010R - Manual (Page 80)

2-50 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
If a fatal interrupt occurs while masked, SCRIPTS halts. The appropriate
bit in the
DMA Status (DSTAT) , SCSI Interrupt Status Zero (SIST0) , or
SCSI Interrupt Status One (SIST1) register is set, the SIP or DIP bit in
the Interrupt Status Zero (ISTAT0) register is set, but the INTA/ (or INTB/)
pin is not asserted.
Setting the SIRQD bit in the Interrupt Status One (ISTAT1) register disables
the interrupt pin for the corresponding SCSI function. If an interrupt pin is
already asserted and SIRQD is then set, the interrupt pin remains asserted
until serviced. Further interrupts are blocked from the interrupt pin.
When the LSI53C1010R is initialized, enable all fatal interrupts if
hardware interrupts are being used. If a fatal interrupt is disabled and that
interrupt condition occurs, the SCRIPTS halts and the system never
knows it unless it times out and checks the
Interrupt Status Zero (ISTAT0) ,
Interrupt Status One (ISTAT1) , Mailbox Zero (MBOX0) , and
Mailbox One (MBOX1) registers after a certain period of inactivity.
If ISTAT is being polled instead of using hardware interrupts, then
masking a fatal interrupt makes no difference because the SIP and DIP
bits in the
Interrupt Status Zero (ISTAT0) inform the system of interrupts,
not the INTA/ (or INTB/) pin.
2.2.16.5 Stacked Interrupts
The LSI53C1010R stacks interrupts, if they occur, one after the other. If
the SIP or DIP bits in the
Interrupt Status Zero (ISTAT0) register are set
(first level), then there is already at least one pending interrupt. Any
future interrupts are stacked in extra registers behind the
SCSI Interrupt Status Zero (SIST0) , SCSI Interrupt Status One (SIST1) ,
and DMA Status (DSTAT) registers (second level). When two interrupts
have occurred and the two levels of the stack are full, any further
interrupts set additional bits in the extra registers behind SIST0, SIST1,
and DSTAT. When the first level of interrupts are cleared, all the later
interrupts move into SIST0, SIST1, and DSTAT. After the first interrupt is
cleared, the INTA/ (or INTB/) pin is deasserted for a minimum of three
CLKs; the stacked interrupts move into SIST0, SIST1, or DSTAT; and the
INTA/ (or INTB/) pin is asserted again.
Because a masked nonfatal interrupt does not set the SIP or DIP bits,
interrupt stacking does not occur. A masked, nonfatal interrupt still posts
the interrupt in
SCSI Interrupt Status Zero (SIST0) , but does not assert