Register: 0x4c – Avago Technologies LSI53C1010R User Manual
Page 203
SCSI Registers
4-85
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
than one bit can be set in the RESPID1 and RESPID0
registers. However, the chip can arbitrate with only one
ID value in the
register.
Register: 0x4C
SCSI Test Zero (STEST0)
Read Only
SSAID[3:0]
SCSI Selected As ID
[7:4]
These bits contain the encoded value of the SCSI ID that
the LSI53C1010R SCSI function is selected or reselected
as during a SCSI Selection or Reselection phase. These
bits are read only and contain the encoded value of
16 possible IDs that could select the LSI53C1010R SCSI
function. During a SCSI Selection or Reselection phase
when a valid ID is put on the bus, and the LSI53C1010R
SCSI function responds to that ID, the “selected as” ID is
written into these bits. These bits are used with
and
registers to allow response
to multiple IDs on the bus.
SLT
Selection Response Logic Test
3
This bit is set when the LSI53C1010R SCSI function is
ready to be selected or reselected. This does not take
into account the bus settle delay of 400 ns. This bit is
used for functional test and fault purposes.
ART
Arbitration Priority Encoder Test
2
This bit is always set when the LSI53C1010R SCSI
function exhibits the highest priority ID asserted on the
SCSI bus during arbitration. It is primarily used for chip
level testing. It may be used during low level mode
operation to determine whether the LSI53C1010R SCSI
function won arbitration.
SOZ
SCSI Synchronous Offset Zero
1
This bit indicates that the current synchronous SREQ/,
SACK/ offset is zero. This bit is not latched and may
change at any time. It is used in low level synchronous
7
4
3
2
1
0
SSAID[3:0]
SLT
ART
SOZ
SOM
0
0
0
0
0
x
1
1