Section 2.2.16.4, “masking – Avago Technologies LSI53C1010R User Manual

Page 79

SCSI Functional Description

2-49

Version 2.2

When the LSI53C1010R is operating in the Initiator mode, Interrupt-on-
the-Fly, Function Complete (CMP), Selected (SEL), Reselected (RSL),
General Purpose Timer Expired (GEN), and Handshake-to-Handshake
Timer Expired (HTH) interrupts are nonfatal.

When operating in the Target mode, Interrupt-on-the-Fly, SATN/ active
(M/A), CMP, SEL, RSL, GEN, and HTH are nonfatal. Refer to the
description for the Disable Halt on a Parity/CRC/AIP Error or SATN/
active (Target Mode Only) bit, DHP, in the

SCSI Control One (SCNTL1)

The reason for nonfatal interrupts is to prevent the SCRIPTS from
stopping when an interrupt occurs that does not require service from the
CPU. This prevents an interrupt when arbitration is complete (CMP set),
when the LSI53C1010R is selected or reselected (SEL or RSL set),
when the initiator asserts ATN (target mode: SATN/ active), or when the
General Purpose or handshake-to-handshake timers expire. These
interrupts are not needed for events that occur during high level
SCRIPTS operation.

2.2.16.4 Masking

Masking an interrupt means disabling or ignoring that interrupt. Clearing
bits in the

SCSI Interrupt Enable Zero (SIEN0)

and

SCSI Interrupt Enable One (SIEN1)

registers mask SCSI interrupts.

Clearing bits in the

DMA Interrupt Enable (DIEN)

interrupts. Masking an interrupt after INTA/ (or INTB/) is asserted does
not cause INTA/ (or INTB/) to be negated. How the chip responds to
masked interrupts depends on whether polling or hardware interrupts are
being used; whether the interrupt is fatal or nonfatal; and whether the
chip is operating in the Initiator or Target mode.

If a nonfatal interrupt occurs while masked, SCRIPTS continues. The
appropriate bit in the

SCSI Interrupt Status Zero (SIST0)

SCSI Interrupt Status One (SIST1)

is still set, the SIP bit in the

Interrupt Status Zero (ISTAT0)

is not set, and the INTA/ (or INTB/) pin is

not asserted.