Register: 0x08 – Avago Technologies LSI53C1010R User Manual

Page 155

SCSI Registers

4-37

Version 2.2

Reserved

[7:5]

GPIO

General Purpose I/O

[4:0]

These bits are programmed through the

General Purpose Pin Control (GPCNTL)

inputs, outputs, or to perform special functions. As an
output, these pins can enable or disable external
terminators. It is also possible to program these signals
as live inputs and sense them through a SCRIPTS
register to register Move Instruction. GPIO[3:0] default as
inputs and GPIO4 defaults as an output pin. When
configured as inputs, an internal pull-up is enabled.

LSI Logic software uses the GPIO[1:0] signals to access
serial EEPROM. GPIO1 is used as a clock, with the
GPIO0 pin serving as data.

LSI Logic software also reserves the use of GPIO[4:2]. If
there is a need to use GPIO[4:2], check with LSI Logic
for details.

Register: 0x08

SCSI First Byte Received (SFBR)
Read/Write

SFBR

SCSI First Byte Received

[7:0]

This register contains the first byte received in any
asynchronous information transfer phase. For example,
when an LSI53C1010R SCSI function is operating in the
initiator mode, this register contains the first byte received
in the Message-In, Status, and Data-In phases.

When a Block Move instruction is executed for a particular
phase, the first byte received is stored in this register,
even if the present phase is the same as the last phase.
The first byte received value for a particular input phase
is not valid until after a MOVE instruction is executed.

This register is also the accumulator for register
read modify-writes with the

SCSI First Byte Received (SFBR)

destination. This allows bit testing after an operation.

SFBR