Table 2.5 scsi parity errors and interrupts, 11 dma fifo, Figure2.2 dma fifo sections – Avago Technologies LSI53C1010R User Manual
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Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.11 DMA FIFO
The DMA FIFO is 8 bytes wide by 112–115 transfers deep, depending
on the type and direction of data transfer. The DMA FIFO is illustrated in
. The small FIFO mode (112 bytes) is not supported by the
LSI53C1010R.
Figure 2.2
DMA FIFO Sections
Table 2.5
SCSI Parity Errors and Interrupts
DHP
1
1. DHP = Disable Halt on SATN/ or Parity Error (bit 5
).
PAR
2
2. PAR = Parity Error (bit 0
SCSI Interrupt Enable One (SIEN1)
).
Description
0
0
Halts when a parity error occurs in the target or initiator mode and
does not generate an interrupt.
0
1
Halts when a parity error occurs in the target mode and generates
an interrupt in the target or initiator mode.
1
0
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is not generated.
1
1
Does not halt in target mode when a parity error occurs until the
end of the transfer. An interrupt is generated.
8 Bytes Wide
Byte Lane 7 Byte Lane 6 Byte Lane 5 Byte Lane 4 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0
112–115
Transfers
Deep