Avago Technologies LSI53C1010R User Manual
Page 279
Transfer Control Instructions
5-31
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Interrupt Instruction
The LSI53C1010R can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as defined
by the Phase Compare, Data Compare, and True/False bit
fields. If the comparisons are true, the LSI53C1010R
generates an interrupt by asserting the IRQ/ signal.
The 32-bit address field stored in the
DMA SCRIPTS Pointer Save (DSPS)
register can contain
a unique interrupt service vector. When servicing the
interrupt, this unique status code allows the
Interrupt Service Routine to identify quickly the point at
which the interrupt occurred.
The LSI53C1010R halts and the
register must be written to
before starting any further operation.
Interrupt-on-the-Fly Instruction
The LSI53C1010R can do a true/false comparison of the
ALU carry bit or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, and the
Interrupt-on-the-Fly bit (
Interrupt Status Zero (ISTAT0),
bit 2) is set, the LSI53C1010R asserts the
Interrupt-on-the-Fly bit.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field corresponds to the three SCSI bus phase
signals that are compared with the phase lines latched
when SREQ/ is asserted. Comparisons can be
performed to determine the SCSI phase being driven on
the SCSI bus. The following table describes the possible
combinations and their corresponding SCSI phase.
These bits are only valid when the LSI53C1010R is
operating in the initiator mode. Clear these bits when the
LSI53C1010R is operating in the target mode.