Dma byte counter (dbc) – Avago Technologies LSI53C1010R User Manual
Page 178
4-60
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x24–0x26
DMA Byte Counter (DBC)
Read/Write
DBC
DMA Byte Counter
[23:0]
This 24-bit register determines the number of bytes
transferred in a Block Move instruction. While sending
data to the SCSI bus, the counter is decremented as data
is moved into the DMA FIFO from memory. While
receiving data from the SCSI bus, the counter is
decremented as data is written to memory from the
LSI53C1010R SCSI function. The DBC counter is
decremented each time data is transferred on the PCI
bus. It is decremented by an amount equal to the number
of bytes transferred.
The maximum number of bytes transferred in any one
Block Move command is 16,777,215. The maximum value
that can be loaded into the
register is 0xFFFFFF. If the instruction is a Block Move
and a value of 0x000000 is loaded into the DBC register,
an illegal instruction interrupt occurs if the LSI53C1010R
SCSI function is not in the target mode, Command phase.
The
register also holds the
least significant 24-bits of the first Dword of a SCRIPTS
fetch, and to hold the offset value during Table Indirect
I/O SCRIPTS. For a complete description refer to
Chapter 5, “SCSI SCRIPTS Instruction Set.”
The
power-up value of this register is indeterminate.
23
0
DBC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0