Avago Technologies LSI53C1010R - Manual (Page 166)

4-48 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x14
Interrupt Status Zero (ISTAT0)
Read/Write
This is the only register that is accessible by the host CPU while an
LSI53C1010R SCSI function is executing SCRIPTS (without interfering
in the operation of the function). It polls for interrupts if hardware
interrupts are disabled. Read this register after servicing an interrupt to
check for stacked interrupts.
ABRT Abort Operation 7
Setting this bit aborts the current operation under
execution by the LSI53C1010R SCSI function. If this bit
is set and an interrupt is received, clear this bit before
reading the
DMA Status (DSTAT) register to prevent
further aborted interrupts from being generated. The
sequence to abort any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the Interrupt Status Zero (ISTAT0) register.
4. If the SCSI Interrupt Pending bit is set, read the
SCSI Interrupt Status Zero (SIST0) or
SCSI Interrupt Status One (SIST1) register to
determine the cause of the SCSI Interrupt and return
to Step 2.
5. If the SCSI Interrupt Pending bit is cleared and the
DMA Interrupt Pending bit is set, write 0x00 to
this register.
6. Read the DMA Status (DSTAT) register to verify the
aborted interrupt and to determine whether any
other interrupting conditions have occurred.
SRST Software Reset 6
Setting this bit resets the LSI53C1010R SCSI function.
All operating registers are cleared to their respective
default values and all SCSI signals are deasserted.
7 6 5 4 3 2 1 0
ABRT SRST SIGP SEM CON INTF SIP DIP
0 0 0 0 0 0 0 0