Avago Technologies LSI53C1010R - Manual (Page 294)

6-4 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.2 LVD Receiver
V
CM
+
−
+
+
−
−
V
I
2
V
I
2
+
−
Table 6.5 A and B DIFFSENS SCSI Signals
Symbol Parameter Min Max Unit Test Conditions
V
IH
HVD sense voltage 2.4 5.05 V Note 1
V
S
LVD sense voltage 0.7 1.9 V Note 1
V
IL
SE sense voltage V
SS
−
0.35 0.5 V Note 1
I
OZ
3-state leakage
−
10 10
µ
A 0 V
DD
= 3 Max
1. Functional test specified V
IH
/V
IL
for each mode.
Table 6.6 Input Capacitance
Symbol Parameter Min Max Unit Test Conditions
C
I
Input capacitance of input pads – 7 pF Guaranteed by design
C
IO
Input capacitance of I/O pads – 15 pF Guaranteed by design
C
PCI
Input capacitance of PCI pads – 8 pF Guaranteed by design
C
LVD
Input capacitance of LVD pads – 8 pF 6.5 pF Pad
1.5 pF Package