Aip control one (aipcntl1), Register: 0xbf – Avago Technologies LSI53C1010R User Manual
Page 232
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
PARITYERR
Parity Error Status
0
This bit represents the error status for the parity error.
This bit is set upon a parity error and clears when the
interrupt clears.
Register: 0xBF
AIP Control One (AIPCNTL1)
Read/Write
R
Reserved
[7:4]
DISAIP
Disable AIP Code Generation
3
When set, this bit disables AIP code generation on the
SCSI bus. By default, AIP codes are generated on the
SCSI bus during all asynchronous transfers.
RAIPERR
Reset AIP Error
2
This bit allows an AIP error condition to be reset
manually. Setting this bit clears the AIP error status in
bit 1 of
. Setting this bit
does not clear the live AIP error status in bit 0 of
. The RAIPERR bit is not
self-clearing. It must be written back to zero.
FBAIP
Force Bad AIP Value
1
When set, this bit causes bad AIP values to be sent over
the SCSI bus.
RSQ
Reset AIP Sequence Value
0
When set, this bit causes the sequence value used in the
calculation of the protection code to be reset.
7
4
3
2
1
0
R
DISAIP
RAIPERR
FBAIP
RSQ
0
0
0
0
0
0
0
0