Avago Technologies LSI53C1010R - Manual (Page 380)

IX-4 Index
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
(SSE) 4-5
(SSI) 4-42 , 4-66
(SSID) 4-39
(SSM) 4-68
(SSTAT0) 4-44
(SSTAT1) 4-45
(SSTAT2) 4-46
(START) 4-25
(STD) 4-69
(STEST0) 4-85
(STEST1) 4-86
(STEST2) 4-88
(STEST3) 4-89
(STEST4) 4-91
(STIME0) 4-80
(STIME1) 4-82
(STO) 4-73 , 4-77
(SVID) 4-12
(SWIDE) 4-78
(SXFER) 4-34
(SZM) 4-88
(TC[23:0]) 5-14 , 5-37
(TE) 4-89
(TEMP) 4-56
(TF) 5-33
(TI) 5-20
(TIA) 5-7
(TM) 5-22
(TRG) 4-27
(TSTADD) 4-122
(TSTCHK) 4-122
(TSTSD) 4-122
(TTM) 4-90
(U3EN) 4-103
(UA) 4-117
(UDC) 4-72 , 4-76
(VAL) 4-39
(VER[2:0]) 4-19
(VP) 5-34
(VUE0) 4-31
(VUE1) 4-31
(WATN) 4-26
(WIE) 4-4
(WOA) 4-45
(WRIE) 4-56
(WSR) 4-31
(WSS) 4-31
(XCLKH_DT) 4-103
(XCLKH_ST) 4-103
(XCLKS_DT) 4-104
(XCLKS_ST) 4-104
Numerics
32/64-bit jump 5-33
32-bit addressing 5-7
3-state 3-2
64 Kbytes ROM read cycle 6-56 , 6-57
64-bit
addressing 5-8
addressing in SCRIPTS 2-21
table indirect indexing mode (64TIMOD) 4-95
66 MHz capable 4-6
A
A and B DIFFSENS SCSI signals 6-4
A[6:0] 5-25
A_DIFFSENS 3-11
A_GPIO0 3-16
A_GPIO1 3-16
A_GPIO2 3-16
A_GPIO3 3-16
A_GPIO4 3-16
A_SACK+- 3-12
A_SATN+- 3-12
A_SBSY+- 3-12
A_SCD+- 3-12
A_SDP[1:0]- 3-11
A_SIO+- 3-12
A_SMSG+- 3-12
A_SREQ+- 3-12
A_SRST+- 3-12
A_SSEL+- 3-12
abort operation (ABRT) 4-48
aborted (ABRT) 4-42 , 4-66
absolute maximum stress ratings 6-2
AC characteristics 6-10
ACK64/ 3-7
acknowledge 64 3-7
active termination 2-39
AD[63:0] 3-6
adder sum output (ADDER) 4-70
address and data signals 3-6
address/data bus 2-3
AIP 1-4 , 2-26
control and generation 2-34
control one (AIPCNTL1) 4-114
control zero (AIPCNTL0) 4-113
disable code generation 4-114
enable 4-103
error reset 4-114
error status 4-113
error status live 4-113
force bad value 4-114