Avago Technologies LSI53C1010R User Manual
Page 82
2-52
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
•
In the case of Transfer Control Instructions, when instruction
execution begins, it continues to completion before halting.
•
In the case of a JUMP/CALL WHEN/IF
is updated to the transfer address
before halting.
•
All other instructions may halt before completion.
2.2.16.7 Sample Interrupt Service Routine
The following is a sample of an interrupt service routine for the
LSI53C1010R. It can be repeated if polling is used, or should be called
when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used.
1.
Read
Interrupt Status Zero (ISTAT0)
2.
If the INTF bit is set, write it to a one to clear this status.
3.
If only the SIP bit is set, read
SCSI Interrupt Status Zero (SIST0)
and
SCSI Interrupt Status One (SIST1)
to clear the SCSI interrupt
condition and get the SCSI interrupt status. The bits in the SIST0
and SIST1 tell which SCSI interrupts occurred and determine what
action is required to service the interrupts.
4.
If only the DIP bit is set, read
to clear the
interrupt condition and determine the DMA interrupt status. The bits
in the DSTAT register indicate which DMA interrupts occurred and
determine what action is required to service the interrupts.
5.
If both the SIP and DIP bits are set, read
SCSI Interrupt Status Zero (SIST0)
,
SCSI Interrupt Status One (SIST1)
, and
to clear
the SCSI and DMA interrupt condition and determine the interrupt
status. If using 8-bit reads of the SIST0, SIST1, and DSTAT registers
to clear interrupts, insert a 12 clock delay between the consecutive
reads to ensure that the interrupts clear properly. Both the SCSI and
DMA interrupt conditions should be handled before leaving the Interrupt
Service Routine (ISR). It is recommended that the DMA interrupt is
serviced before the SCSI interrupt, because a serious DMA interrupt
condition could influence how the SCSI interrupt is acted upon.
6.
When using polled interrupts, go back to step 1 before leaving the
ISR in case any stacked interrupts moved in when the first interrupt
was cleared. When using hardware interrupts, the INTA/ (or INTB/)
pin is asserted again if there are any stacked interrupts. This should
cause the system to re-enter the interrupt service routine.