Interrupt status one (istat1), Register: 0x15 – Avago Technologies LSI53C1010R User Manual
Page 169
SCSI Registers
4-51
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
DIP
DMA Interrupt Pending
0
This status bit is set when an interrupt condition is detected
in the DMA portion of the LSI53C1010R SCSI function.
The following conditions cause a DMA interrupt to occur:
•
A PCI parity error is detected
•
A bus fault is detected
•
An abort condition is detected
•
A SCRIPTS instruction is executed in the single-step
mode
•
A SCRIPTS interrupt instruction is executed
•
An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the
register.
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
R
Reserved
[7:3]
FLSH
Flushing
2
If this bit is set, the chip is flushing data from the DMA
FIFO. If cleared, no flushing is occurring. This bit is read
only. Writes do not affect the value of this bit.
SRUN
SCRIPTS Running
1
If this bit is set, the SCRIPTS engine is currently fetching
and executing SCRIPTS instructions. If it is cleared, the
SCRIPTS engine is not active. This bit is read only.
Writes do not affect the value of this bit.
SI
SYNC_IRQD
0
Setting this bit disables the INTA/ pin for Function A and
the INTB/ pin for Function B, except for the SCSI gross
error, bus fault, residual data in SCSI FIFO, and data
underflow interrupts. Clearing this bit enables normal
operation of the INTA/ (or INTB/) pin. If the INTA/
7
3
2
1
0
R
FLSH
SRUN
SI
0
0
0
0
0
0
0
0