Avago Technologies LSI53C1010R - Manual (Page 355)

SCSI Timing Diagrams 6-65
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.40 Initiator and Target DT Synchronous Transfer
Table 6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers) Quadrupled
40 MHz Clock
Symbol Parameter Min Max Unit
t
DT1
Send SREQ/ assertion pulse width 11.5 – ns
t
DT2
Send SREQ/ deassertion pulse width 11.5 – ns
t
DT1
Receive SREQ/ assertion pulse width 10 – ns
t
DT2
Receive SREQ/ deassertion pulse width 10 – ns
t
DT3
Send data setup to SREQ/ transition 5 – ns
t
DT4
Send data hold from SREQ/ transition 5 – ns
t
DT5
Receive data setup to SREQ/ transition 1.25 – ns
t
DT6
Receive data hold from SREQ/ transition 1.25 – ns
t
DT7
Send CRC Request Setup to SREQ/ transition 15 – ns
t
DT8
Send CRC Request Hold to SREQ/ transition 5 – ns
t
DT9
Receive CRC Request Setup to SREQ/ transition 8.25 – ns
t
DT10
Receive CRC Request Hold to SREQ/ transition 1.25 – ns
t
DT1
SREQ/SACK
Send Data
(SD[15:0]/)
Receive Data
(SD[15:0]/)
t
DT2
t
DT5
Send CRC
Request
(DP0/)
Receive CRC
Request
(DP0/)
t
DT3
t
DT4
t
DT6
t
DT5
t
DT6
t
DT3
t
DT4
t
DT8
t
DT7
t
DT10
t
DT9