Avago Technologies LSI53C1010R - Manual (Page 196)

4-78 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Acknowledge-to-Acknowledge (initiator) period. Refer to
the description of the
SCSI Timer Zero (STIME0) register,
bits [7:4], for details on the handshake-to-handshake timer.
Register: 0x44
Reserved
This register is reserved.
Register: 0x45
SCSI Wide Residue (SWIDE)
Read/Write
SWIDE SCSI Wide Residue [7:0]
After a wide SCSI data receive operation, this register
contains a residual data byte if the last byte received was
never sent across the DMA bus. It represents either the
first data byte of a subsequent data transfer, a residue
byte which should be cleared when an Ignore Wide
Residue message is received, or an overrun data byte.
The power-up value of this register is indeterminate.
Register: 0x46
Reserved
This register is reserved.
7 0
R
x x x x x x x x
7 0
SWIDE
0 0 0 0 0 0 0 0
7 0
R
x x x x x x x x