Avago Technologies LSI53C1010R - Manual (Page 287)

Load and Store Instructions 5-39
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
TEMP Register [31:0]
These bits contain the destination address for the
Memory Move.
If the destination address is in the 64-bit address space,
the bits are contained in the
Memory Move Write Selector (MMWS) register.
5.7 Load and Store Instructions
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The load and store instructions are represented by two Dword opcodes.
The first Dword contains the
DMA Command (DCMD) and
DMA Byte Counter (DBC) register values. The second Dword contains
the DMA SCRIPTS Pointer Save (DSPS) value. This is either the actual
memory location of where to load/store, or the offset from the
Data Structure Address (DSA) , depending on the value of bit 28
(DSA Relative).
For load operations where the data is read from the 64-bit address
space, the upper Dword of address resides in the
Memory Move Read Selector (MMRS) register. For store operations
where the data is written to the 64-bit address space, the upper Dword
of address resides in the
Memory Move Write Selector (MMWS) register.
A maximum of 4 bytes may be moved with these instructions. The
register address and memory address must have the same byte
alignment, and the count set such that it does not cross Dword
boundaries. The memory address may not map back to the chip,
excluding RAM and ROM. If it does, a PCI read/write cycle occurs (the
data does not transfer to/from the chip), and the chip issues an interrupt
(Illegal Instruction Detected) immediately following.
31 0
MMWS Register