Avago Technologies LSI53C1010R - Manual (Page 383)

Index IX-7
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
disable
64-bit master operation 4-95
64-bit slave cycles 4-95
AIP code generation 4-114
auto FIFO clear (DISFC) 4-94
CRC checking 4-121
CRC protocol checking 4-121
dual address cycle (DDAC) 4-95
halt on parity/CRC error or ATN (DHP) 4-28
internal SCRIPT RAM cycles 4-94
pipe req (DPR) 4-94
single initiator response (DSI) 4-89
disconnect 2-19
instruction 5-17
last 4-47
DMA
burst length 4-63
byte counter (DBC) 4-60
command (DCMD) 4-61
control (DCNTL) 2-7 , 2-8 , 2-9 , 4-67
destination I/O-memory enable 4-64
FIFO 2-9 , 2-36 , 2-47 , 4-59
byte count (DFBC) register 4-124
byte empty 4-53
byte full 4-53
byte lane 4-58
clear 4-56
empty (DFE) 4-41
flush 4-55
sections 2-36
interrupt 2-51
enable (DIEN) 2-35 , 2-48 , 4-66
pending (DIP) 4-51
mode (DMODE) 2-7 , 2-8 , 2-9 , 2-13 , 2-32 , 4-63
next address (DNAD) 4-61
next address 64 (DNAD64) 4-102
SCRIPTS
pointer (DSP) 4-62
pointer save (DSPS) 4-62
source I/O-memory enable 4-64
status (DSTAT) 2-35 , 2-48 , 2-50 , 2-51 , 2-52
status register (DSTAT) 4-41
domain validation 1-5 , 2-23
double transition
clocking 2-23
transfer rates 4-109
transfer waveforms 4-107 , 4-108
download mode 2-61
DSA
relative 5-40
relative selector (DRS) 4-101
DSPS register 5-38
DSTAT 2-48
DT data-in 2-23
DT data-out 2-23
DT transfers
configuration 2-44
dual address cycles 2-21
command 2-8
dynamic block move selector (DBMS) 4-102
E
EEPROM 2-60 , 3-22
default download mode 2-60
enable
64-bit
direct BMOV (EN64DBMV) 4-96
table indirect BMOV (EN64TIBMV) 4-96
AIP 4-103
asynchronous information protection 4-103
bus mastering (EBM) 4-4
CRC auto seed 4-122
fetch 4-79
I/O space (EIS) 4-4
jump on nondata phase mismatches (ENNDJ) 4-94
master 4-79
memory space (EMS) 4-4
parity
checking 2-34
checking (EPC) 4-26
error response (EPER) 4-3
phase mismatch jump (ENPMJ) 4-93
read
line (ERL) 4-65
multiple (ERMP) 4-65
response to
reselection (RRE) 4-33
selection (SRE) 4-33
Ultra160 transfer 4-103
wide SCSI (EWS) 4-32
ENABLE66 3-5
enabling cache mode 2-13
encoded
chip SCSI ID 4-33
destination SCSI ID
(ENC[3:0]) 4-36
(ENID[3:0]) 4-39
SCSI destination ID 5-22
entry storage address (ESA) 4-118
error reporting signals 3-8
even parity 2-34
expansion ROM
base address 4-14
enable 4-14