Avago Technologies LSI53C1010R - Manual (Page 140)

4-22 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
4.2 SCSI Registers
The control registers for the SCSI core are directly accessible from the
PCI bus using Memory or I/O mapping. SCSI Function A and SCSI
Function B contain the same register set with identical default values,
except the Interrupt Pin registers. The address map of the SCSI registers
is shown in
Table 4.2 .
The eight 32-bit, phase mismatch registers contain the byte count and
addressing information required to update the Direct, Indirect, or Table
Indirect BMOV instructions with new byte counts and addresses. The phase
mismatch registers are the
Phase Mismatch Jump Address One (PMJAD1) ,
Phase Mismatch Jump Address Two (PMJAD2) ,
Remaining Byte Count (RBC) , Updated Address (UA) ,
Entry Storage Address (ESA) , Instruction Address (IA) ,
SCSI Byte Count (SBC) , and the Cumulative SCSI Byte Count (CSBC)
registers. All of the phase mismatch registers can be read or written using
the Load and Store SCRIPTS instructions, Memory-to-Memory Moves,
Read/Write SCRIPTS instructions, or the CPU with SCRIPTS not running.
Note: The only registers that the host CPU can access while the
LSI53C1010R is executing SCRIPTS are the
Interrupt Status Zero (ISTAT0) , Interrupt Status One (ISTAT1) ,
Mailbox Zero (MBOX0) , and Mailbox One (MBOX1) registers;
attempts to access other registers interfere with the operation
of the chip. However, all operating registers are accessible
with SCRIPTS. All read data is synchronized and stable
when presented to the PCI bus.
Note: Do not access reserved bits or registers.