Avago Technologies LSI53C1010R - Manual (Page 73)

SCSI Functional Description 2-43
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
DT edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1010R receives outbound
REQs, ACKs, or data.
Bit 2, XCLKH_ST (Extra Clock of Data Hold on ST transfer edge), adds
a clock of data hold to synchronous DT or ST SCSI transfers on the ST
edge. This bit impacts DT and ST transfers because it affects data hold
to the ST edge. Setting this bit reduces the synchronous transfer send
rate but does not reduce the rate at which the LSI53C1010R receives
outbound REQs, ACKs, or data.
Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT transfer edge), adds
a clock of data setup to synchronous DT SCSI transfers on the DT edge.
This bit only impacts DT transfers because it only affects data hold to the
DT edge. Setting this bit reduces the synchronous transfer send rate but
does not reduce the rate at which the LSI53C1010R receives outbound
REQs, ACKs, or data.
Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST transfer edge), adds
a clock of data setup to synchronous DT or ST SCSI transfers on the ST
edge. This bit impacts DT and ST transfers because it affects data hold
to the ST edge. Setting this bit reduces the synchronous transfer send
rate but does not reduce the rate at which the LSI53C1010R receives
outbound REQs, ACKs, or data.
2.2.15.3 Determining the Data Transfer Rate
The synchronous receive rate can be calculated using the following
formula:
Note: The receive rate is independent of the settings of the
XCLKS_DT, XCLKS_ST, XCLKH_DT, XCLKH_ST bits.
Receive Rate (DT)
Input Clock Rate
SCF Divisor 2
× ( )
---------------------------------------------- (Megatransfers/s) =
Receive Rate (ST)
Input Clock Rate
SCF Divisor 4
× ( )
---------------------------------------------- (Megatransfers/s) =