Avago Technologies LSI53C1010R - Manual (Page 346)

6-56 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.33
≤
64 Kbytes ROM Read Cycle
Table 6.37
≤
64 Kbytes ROM Read Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ HIGH 25 – ns
t
12
Address hold from MAS/ HIGH 15 – ns
t
13
MAS/ pulse width 25 – ns
t
14
MCE/ LOW to data clocked in 150 – ns
t
15
Address valid to data clocked in 205 – ns
t
16
MOE/ LOW to data clocked in 100 – ns
t
17
Data hold from address, MOE/, MCE/ change 0 – ns
t
18
Address out from MOE/, MCE/ HIGH 50 – ns
t
19
Data setup to CLK HIGH 5 – ns
CLK
(Driven by System)
1 2 3 4 5 6 7 8 9 10
MAD
(Addr drvn by LSI53C1010R;
High Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
t
11
11 12 13 14 15
Read
Data
t
19
Data drvn by Mem)
t
12
t
13 t
15
t
14
Valid
t
17
t
16
t
18