Avago Technologies LSI53C1010R - Manual (Page 59)

SCSI Functional Description 2-29
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
– Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT Transfer Edge)
is set to add a clock of data setup to synchronous DT SCSI
transfers on the DT edge. This bit only impacts DT transfers
because it affects data setup to the DT edge.
– Bit 0, XCLKS_ST (Extra Clock of Data Setup on ST Transfer
Edge) is set to add a clock of data setup to synchronous DT or
ST SCSI transfers on the ST edge. This bit impacts both ST and
DT transfers because it affects data setup to the ST edge.
Note. The XCLKH_DT, XCLKH_ST, XCLKS_DT, and XCLKS_ST
bits do not affect CRC timings.
•
The AIP Control Zero (AIPCNTL0) register:
– Bits [7:3] are reserved.
– Bit 2, AIPERR_LIVE (AIP Error Status Live), represents the live
error status for the AIP checking logic. This is not a latched value.
– Bit 1, AIPERR (AIP Error Status), represents the error status for
the AIP checking logic.
– Bit 0, PARITYERR (Parity Error), represents the error status for
the parity error.
•
The AIP Control One (AIPCNTL1) register:
– Bits [7:4] are reserved.
– Bit 3, DISAIP (Disable AIP Code Generation), disables the AIP
code generation on the SCSI bus.
– Bit 2, RAIPERR (Reset AIP Error), allows an AIP error condition
to be reset manually.
– Bit 1, FBAIP (Force Bad AIP Value), causes bad AIP values to
be sent over the SCSI bus.
– Bit 0, RSQ (Reset AIP Sequence Value), causes the sequence
value used in the calculation of the protection code to be reset.
•
The CRC Pad Byte Value (CRCPAD) register:
– Bits [15:0], the CRC Pad byte value, contain the value placed
onto the bus for the CRC pad bytes.
•
The CRC Control Zero (CRCCNTL0) register:
– Bit 7, DCRCC (Disable CRC Checking), is set to cause the
internal logic to not check or report CRC errors during Ultra160
transfers. The device continues to calculate and send CRCs as
requested by the target according to the SPI-3 specification.