Avago Technologies LSI53C1010R - Manual (Page 25)

Summary of LSI53C1010R Benefits 1-7
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
1.6 Summary of LSI53C1010R Benefits
This section provides a summary of the LSI53C1010R features and
benefits. It contains information on SCSI Performance, PCI Performance,
Integration, Ease of Use, Flexibility, Reliability, and Testability.
1.6.1 SCSI Performance
The LSI53C1010R:
•
Performs wide, Ultra160 SCSI synchronous data transfers as fast as
160 Mbytes/s on each SCSI channel for a total of 320 Mbytes/s using
DT clocking.
•
Supports CRC checking and generation in DT phases.
•
Protects nondata phases with AIP.
•
Supports domain validation:
– Basic (level 1)
– Enhanced (level 2)
– Margined (level 3)
•
Includes integrated LVDlink universal transceivers:
– Supports SE and LVD signals.
– Allows greater device connectivity and longer cable length.
– LVDlink transceivers save the cost of external differential
transceivers.
– Supports a long-term performance migration path.
•
Bursts of up to 512 bytes across the PCI bus with an independent
896–920 byte FIFO on each SCSI channel.
•
Includes two separate SCSI channels on one chip.
•
Handles phase mismatches in SCRIPTS without interrupting the
system processor.
•
Includes an on-chip SCSI clock quadrupler that allows the chip to
achieve Ultra160 SCSI transfer rates with an input frequency of
40 MHz.