Avago Technologies LSI53C1010R - Manual (Page 376)

B-4 External Memory Interface Diagram Examples
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure B.4 512 Kbyte Interface with 150 ns Memory
LSI53C1010R
MOE/
D[7:0] 8
MAD[7:0]
Bus
CK
Q[7:0]
8
A[7:0]
QE
D[7:0]
CK
Q[7:0]
QE
8
A[15:8]
8
V
DD
MAS0/
MAS1/
8
Note: MAD2 pulled LOW internally. MAD bus sense logic enabled for 512 Kbytes of slow memory (150 ns
devices, additional time required for HCT139 @ 66 MHz). The HCT374s may be replaced with HCT377s.
HCT374
HCT374
GPIO4
MWE/
VPP
Control
+ 12 V
VPP
Optional – for Flash Memory only, not
required for EEPROMs.
D[7:0]
MAD3 4.7 K
D[2:0]
CK
Q0
Q2
3
HCT377
MAD[2:0]
Bus
E
MAD1 4.7 K
MAD3 4.7 K
OE
WE
D[7:0]
A0
A16
.
.
.
OE
WE
D[7:0]
A0
A16
.
.
.
OE
WE
D[7:0]
A0
A16
.
.
.
OE
WE
D[7:0]
A0
A16
.
.
.
A
B
GB
Y0
Y1
Y2
Y3
MCE/
HCT139
CE CE CE CE
27C010-15/28F010–15 Sockets