Avago Technologies LSI53C1010R - Manual (Page 329)

PCI and External Memory Interface Timing Diagrams 6-39
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.25 External Memory Read (Cont.)
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1010R)
STOP/
(Driven by LSI53C1010R)
DEVSEL/
(Driven by LSI53C1010R)
AD[31:0]
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
11 12 13 14 15 16 17 18 19 20
LSI53C1010R Data)
Data
Out
LSI53C1010R Data)
MAD
(Addr driven by LSI53C1010R;
MAS1/
(Driven by LSI53C1010R)
MAS0/
(Driven by LSI53C1010R)
MCE/
(Driven by LSI53C1010R)
MOE/
(Driven by LSI53C1010R)
MWE/
(Driven by LSI53C1010R)
t
3
t
2
t
2
t
15
21
t
3
Out
t
3
t
3
Data
In
t
19
t
17
t
14
t
16