Avago Technologies LSI53C1010R - Manual (Page 89)

Parallel ROM Interface 2-59
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.3 Parallel ROM Interface
The LSI53C1010R supports up to 1 Mbyte of external memory in binary
increments from 16 Kbytes to allow the use of expansion ROM for add-in
PCI cards. Both functions of the device share the ROM interface. This
interface is designed for low speed operations such as downloading
instruction code from ROM; it is not intended for dynamic activities such
as executing instructions.
System requirements include the LSI53C1010R, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 k
Ω
pull-up resistors on the MAD bus
require HC or HCT external components to be used. Pull-up resistors on
the 8-bit bidirectional memory bus at power-up determine the memory
size and speed. The LSI53C1010R senses this bus shortly after the
release of the Reset signal and configures the Expansion ROM Base
Address register and the memory cycle state machines for the
appropriate conditions.
The LSI53C1010R supports a variety of sizes and speeds of expansion
ROM. An example set of interface drawings is in
Appendix B, “External Memory Interface Diagram Examples.” The
encoding of pins MAD[3:1] allows the user to define how much external
memory is available to the LSI53C1010R.
Table 2.7 shows the memory
space associated with the possible values of MAD[3:1]. The MAD[3:1]
pins are fully described in
Chapter 3, “Signal Descriptions.”
Table 2.7 Parallel ROM Support
MAD[3:1] Available Memory Space
000 16 Kbytes
001 32 Kbytes
010 64 Kbytes
011 128 Kbytes
100 256 Kbytes
101 512 Kbytes
110 1024 Kbytes
111 No external memory present, ROM interface disabled