Avago Technologies LSI53C1010R - Manual (Page 239)

SCSI Registers 4-121
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0xE0–0xE1
CRC Pad Byte Value (CRCPAD)
Read/Write
CRCPBV CRC Pad Byte Value [15:0]
This register contains the value placed onto the bus for
the CRC pad bytes.
Register: 0xE2
CRC Control Zero (CRCCNTL0)
Read/Write
DCRCC Disable CRC Checking 7
Setting this bit causes the internal logic not to check or
report CRC errors during Ultra160 transfers. The
LSI53C1010R continues to calculate and send CRCs as
requested by the target according to the SPI-3
specification.
DCRCPC Disable CRC Protocol Checking 6
Setting this bit causes the internal logic to neither check nor
report CRC protocol errors during Ultra160 transfers. The
LSI53C1010R continues to calculate and send CRCs as
requested by the target according to the SPI-3 specification
but does not set an SGE interrupt if a CRC protocol error
occurs. This bit should not be set in normal operations.
R Reserved [5:0]
15 0
CRCPBV
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 0
DCRCC DCRCPC R
0 0 0 0 0 0 0 0