Avago Technologies LSI53C1010R - Manual (Page 125)

PCI Configuration Registers 4-7
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x09–0x0B
Class Code (CC)
Read Only
CC Class Code [23:0]
This 24-bit register identifies the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register-level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.
Register: 0x0C
Cache Line Size (CLS)
Read/Write
CLS Cache Line Size [7:0]
This register specifies the system cache line size in units
of 32-bit words. The value in this register is used by the
device to determine whether to use Write and Invalidate
or Write commands for performing write cycles, and
whether to use Read, Read Line, or Read Multiple
commands for performing read cycles as a bus master.
Devices participating in the caching protocol use this field
to determine when to retry burst accesses at cache line
boundaries. These devices can ignore the PCI cache
support lines (SDONE and SB0/) if this register is set
to 0. If this register is programmed to a number that is
not a power of 2, the device does not use PCI
performance commands to execute data transfers.
23 0
CC
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 0
CLS
0 0 0 0 0 0 0 0