Avago Technologies LSI53C1010R - Manual (Page 209)

SCSI Registers 4-91
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
register causes the SCSI parity bit to be checked, and
causes a parity error interrupt if the data is invalid. The
power-up values are indeterminate.
Register: 0x52
SCSI Test Four (STEST4)
Read Only
SMODE[1:0] SCSI Mode [7:6]
These bits contain the encoded value of the SCSI
operating mode that is indicated by the voltage level
sensed at the DIFFSENS pin. The incoming SCSI signal
goes to a pair of analog comparators that determine the
voltage window of the DIFFSENS signal. These voltage
windows indicate LVD, SE, or HVD operation. The bit
values are defined in the following table. When the HVD
mode is detected, all of the LSI53C1010R 3-state outputs
go to the high impedance state.
R Reserved [5:0]
7 6 5 0
SMODE[1:0] R
x x 0 0 0 0 0 0
SMODE [1:0] Operating Mode
00 Reserved
01 High Impedance State
10 SE SCSI
11 LVD SCSI