Avago Technologies LSI53C1010R - Manual (Page 119)

LSI53C1010R PCI to Dual Channel Ultra160 SCSI Multifunction Controller 4-1
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Chapter 4
Registers
This section contains descriptions of all LSI53C1010R registers. The
term “set” refers to bits programmed to a binary one. Similarly, the term
“cleared” refers to bits programmed to a binary zero. Do not access
reserved bits. Reserved bit functions may change at any time. Unless
otherwise indicated, all bits in the registers are active HIGH; the feature
is enabled by setting the bit. The bottom row of every register diagram
presents the default register values, which are enabled after the chip is
powered on or reset.
This chapter contains the following sections:
•
Section 4.1, “PCI Configuration Registers”
•
Section 4.2, “SCSI Registers”
•
Section 4.3, “SCSI Shadow Registers”
4.1 PCI Configuration Registers
To access the PCI Configuration registers, perform a configuration read or
write to a device with its IDSEL pin asserted. The appropriate address
value is in AD[10:8] during the address phase of the transaction. SCSI
Function A is identified by a binary value of 0b000, and SCSI Function B
by a value of 0b001. Each SCSI function contains the same register set
with identical default values, except the
Interrupt Pin (IP) register. Table 4.1
shows the PCI configuration registers implemented in the LSI53C1010R.
All PCI-compliant devices, such as the LSI53C1010R, support Vendor ID ,
Device ID , Command , and Status registers. Support of other PCI-compliant
registers is optional. In the LSI53C1010R, registers that are not supported
are not writable and return all zeros when read. Only those registers and
bits that are currently supported by the LSI53C1010R are described in this
chapter. Do not access bits marked as Reserved.