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7 opcode fetch burst capability, Opcode fetch burst capability – Avago Technologies LSI53C1010R User Manual

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Functional Description

Version 2.2

Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.

To ensure the LSI53C1010R always operates from the current version of
the SCRIPTS instruction, the contents of the prefetch unit may be
flushed under certain conditions. The contents of the prefetch unit are
automatically flushed under the following conditions:

On every Memory Move instruction.

The Memory Move instruction places modified code into memory. To
assure the device executes recent modifications, the prefetch unit
flushes its contents and reloads the code each time an instruction is
issued. To avoid inadvertently flushing the prefetch unit contents, use
the No Flush option for all Memory Move operations that do not
modify code within the next 8 Dwords. For more information refer to

Chapter 5, “SCSI SCRIPTS Instruction Set.”

On every Store instruction.

The Store instruction may also place modified code directly into
memory. To avoid inadvertently flushing the prefetch unit contents,
use the No Flush option for all Store operations that do not modify
code within the next 8 Dwords.

On every write to the

DMA SCRIPTS Pointer (DSP)

register.

On all Transfer Control instructions, when the transfer conditions
are met.

This is necessary because the next instruction to be executed is not
the sequential next instruction in the prefetch unit.

When the Prefetch Flush bit (

DMA Control (DCNTL)

register, bit 6)

is set.

The unit flushes whenever this bit is set. This bit is self-clearing.

2.2.7 Opcode Fetch Burst Capability

Setting the Burst Opcode Fetch Enable bit (bit 1) in the

DMA Mode (DMODE)

register (0x38) causes the LSI53C1010R to burst

in the first two Dwords of all instruction fetches. If the instruction is a
Memory-to-Memory Move, the third Dword is accessed in a separate
ownership. If the instruction is an indirect type, the additional Dword is
accessed in a subsequent bus ownership. If the instruction is a
Table Indirect Block Move, the device uses two accesses, each a two
Dword burst, to obtain the four Dwords required.