Avago Technologies LSI53C1010R User Manual
Page 205
SCSI Registers
4-87
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
QSEL
SCLK Quadrupler Select
2
This bit, when set, selects the output of the internal clock
quadrupler as the internal SCSI clock. When cleared, this
bit selects the clock presented on SCLK as the internal
SCSI clock. Refer to
Chapter 2, “Functional Description,”
for information concerning the operation of the
quadrupler.
IRM[1:0]
Interrupt Routing Mode
[1:0]
The LSI53C1010R supports four different interrupt
routing modes. These modes are described in the
following table. Each SCSI core within the chip can be
configured independently. Mode 0, the default mode, is
compatible with RAID upgrade products.
Mode
Bits [1:0] Operation
0
00
If the INT_DIR/ input pin is low, interrupts
are signaled on ALT_INTx/. Otherwise,
interrupts are signaled on both INTx/ and
ALT_INTx/.
1
01
Interrupts are only signaled on INTx/, not
ALT_INTx/. The INT_DIR/ input pin is
ignored.
2
10
Interrupts are only signaled on
ALT_INTx/. The INT_DIR/ input pin is
ignored.
3
11
Interrupts are signaled on both INTx/ and
ALT_INTx/. The INT_DIR input pin is
ignored.