Avago Technologies LSI53C1010R - Manual (Page 381)

Index IX-5
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
options 2-34
reset sequence value 4-114
ALT_INTA/ 3-9
ALT_INTB/ 3-9
arbitration
full 4-25
immediate 4-29
in progress (ARBIP) 4-44
lost 4-44
mode bits 1 and 0 (ARB[1:0]) 4-24
priority encoder test (ART) 4-85
signals 3-8
simple 4-24
won 4-45
assert
even SCSI parity (force bad parity) (AESP) 4-29
SATN/ on parity/CRC error (AAP) 4-27
SCSI
ACK/ signal (ACK) 4-38 , 4-40
ATN/ signal (ATN) 4-38 , 4-40
BSY/ signal (BSY) 4-38 , 4-40
C_D/ signal (C_D) 4-39 , 4-40
data bus (ADB) 4-28
I_O/ signal (I/O) 4-39 , 4-40
MSG/ signal (MSG) 4-38 , 4-40
REQ/ signal (REQ) 4-38 , 4-40
RST/ signal (RST) 4-29
SEL/ signal (SEL) 4-38 , 4-40
asynchronous information protection 2-26
enable 4-103
asynchronous SCSI
receive 2-38
send 2-37
aux_current 4-19
B
B_DIFFSENS 3-14
B_GPIO 3-17
B_GPIO0 3-17
B_GPIO2 3-17
B_GPIO3 3-17
B_GPIO4 3-17
B_SACK+- 3-15
B_SATN+- 3-15
B_SBSY+- 3-15
B_SCD+- 3-15
B_SD[15:0]+- 3-13
B_SDP[1:0]+- 3-13
B_SIO+- 3-15
B_SMSG+- 3-15
B_SREQ+- 3-15
B_SRST+- 3-15
B_SSEL+- 3-15
back-to-back read
32-bit address and data 6-25
back-to-back write
32-bit address and data 6-27
base address register
four 4-11
one 2-4 , 4-9
three 4-10
zero 2-4 , 4-9
base address register two 4-10
base address table indirect 4-47
BCH 2-26
bidirectional 3-2
signals 6-5 , 6-6
BIOS 2-3
bits used for parity control and generation 2-34
block move 2-10
instructions 5-5
bridge support extensions (BSE[7:0]) 4-21
burst
length (BL[1:0]) 4-63
length bit 2 (BL2) 4-59
opcode fetch enable (BOF) 4-65
size selection 2-7
burst opcode fetch
32-bit address and data 6-23
burst read
32-bits address and data 6-29
64-bit address and data 6-31
burst write
32-bit address and data 6-33
64-bit address and data 6-35
bus
command and byte enables 3-6
fault (BF) 4-41 , 4-66
byte
count 5-41
empty in DMA FIFO (FMT[7:0]) 4-53
full in DMA FIFO (FFL[7:0]) 4-53
C
C_BE[3:0]/ 2-3
C_BE[7:0]/ 3-6
cache line size
(CLS) 2-8
(CLS[7:0]) 4-7
enable (CLSE) 2-8 , 4-67
register 2-7 , 2-11
cache line size register 4-7
cache mode, See PCI cache mode 2-11
call instruction 5-30